Superscalar data processing machines represent the state-of-the-art in the field of computing systems. These machines are able to execute two or more instruction in parallel under certain conditions. A good example the Intel.RTM. Pentium.TM. processor which is designed to execute pairs instructions if the instructions are of a certain type and if there are no register dependencies. This latter requirement means that data produced by the operation of one instruction cannot be specified as an input operand for the second instruction. In other words, if one instruction utilizes the output of another instruction, the two instructions must execute serially in the proper order.
As one might expect, there has been a great deal of effort in the data processing art focused upon solving the problem of how to best determine the existence of data conflicts in a sequence of pipelined instructions. By way of example, U.S. Pat. No. 4,969,117 discloses a sequential processor which includes circuitry for determining a correct ordering sequence for instructions.
The problem of resolving data dependencies in a superscalar processor has recently become more cumbersome with the advent of speculative execution architectures. These machines are not only are capable of executing instructions in parallel, but also have the ability to execute instructions out-of-order; that is, in an order other than the programmed order with which instructions are issued within the machine. Out-of-order data processors generally execute instructions based upon data and resource availability, and then restore the original program order during a retirement process. The retirement process "retires" instructions by writing their results to a set of architectural registers at the appropriate time.
The present invention deals with the interaction between instructions in an advanced pipelined microprocessor. As will be seen, the invention provides a method for maximizing the number of instructions that can be processed simultaneously within a processor's execution unit. By resolving dependencies--and through the use of mechanisms such as bypassing and scoreboarding--the invention offers faster processing speed for all types of machines (e.g., RISC or CISC).